1. Field of the Invention
The present invention relates to a semiconductor memory device and operation method thereof and, more specifically, to a semiconductor memory device and operation method thereof in which data stored in a memory cell is read by utilizing potential difference between two bit lines.
2. Description of the Background Art
Generally, in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), memory cells are arranged in a plurality of rows and columns, and two bit lines are provided corresponding to each column of the memory cells.
In data reading, potential of one of the two bit lines corresponding to the column including the memory cell from which data is to be written rises, and potential of the other one lowers. Potential of which one of the two bit line rises (or lowers) depends on the data stored in the memory cell. Therefore, a signal provided by amplifying the potential difference between these two bit lines is regarded as the data stored in the memory cell.
FIG. 10 is a schematic block diagram showing the whole structure of a conventional DRAM. A general structure and operation of the conventional DRAM will be described with reference to FIG. 10.
In the following description in this specification, a low-active signal is represented by a reference character with "/", and a signal line transmitting the low-active signal is represented by a reference character with "/".
A memory cell array 61 includes memory cells MCs arranged in a plurality of rows and columns, a plurality of word lines WL provided corresponding to the plurality of rows, and two bit lines BL and /BL provided corresponding to each of the plurality of columns. All bit line pairs BL and /BL are connected to a sense amplifier group 60 and a bit line equalizer 59.
The operation of the DRAM when data is read from memory cell array 61 is as follows.
When data is read from memory cell array 61 address buffer 54 takes and buffers external address signals A0-An and applies column address signals CA0-CA(n-1) designating one of the memory cell columns in memory cell array 61, row address signals RA0-RA(n-1) designating one of the memory cell rows of the memory cell array 61, and a signal An of the most significant bit of the external address signals A0-An to column decoder 57, row decoder 58 and I/O control circuit 53, respectively.
Each word line WL is commonly connected to all memory cells MCs arranged in the corresponding row, and each bit line BL, /BL is commonly and alternately connected to the memory cells MCs arranged in the corresponding column.
Row decoder 58 decodes row address signals RA0-RA(n-1) from address buffer 65, and activates to a high level one word line provided corresponding to the row of the memory cells designated by the row address signal out of the word lines WL in memory cell array 61. Consequently, it becomes possible to exchange data signal between each memory cell MC connected to the activated word line WL corresponding to the row address signal and the bit line BL or /BL connected to the memory cell MC. The potential of the bit line BL or /BL connected to the memory cell MC changes dependent on the data stored in each memory cell MC connected to the one word line WL.
Sense amplifier group 60 includes a plurality of sense amplifiers (not shown) provided corresponding to all bit line pairs BL, /BL in memory cell array 61. Each sense amplifier amplifies potential difference between two bit lines BL and /BL constituting the corresponding bit line pair BL, /BL.
I/O gate.multidot.I/O line 62 includes a pair of I/O lines transmitting signals of complementary potential levels, and an I/O gate constituted by a plurality of transfer gates provided between the I/O line pair and the respective sense amplifiers in sense amplifier group 60.
Column decoder 67 decodes column address signals CA0-CA(n-1) from address buffer 54 and outputs a signal for controlling the transfer gate such that only the sense amplifier connected to one pair provided corresponding to the column of the memory cells designated by the column address signal out of the bit line pairs BL, /BL in memory cell array 61 is electrically connected to the I/O line pair.
An I/O line potential control circuit 5 amplifies potential difference between two I/O lines constituting the I/O line pair and applies it to data output buffer 56.
Data output buffer 56 amplifies an output signal from I/O line potential control circuit 5 and externally outputs the resulting signal as read data from memory cell array 61.
The operation of writing data to memory cell array 61 will be described.
Address buffer 54, column decoder 57, row decoder 58 and I/O gate.multidot.I/O line 62 operate in the same manner as in data reading from memory cell array 61.
A data input buffer 55 amplifies an externally input data signal and applies the same to I/O line potential control circuit 5.
I/O line potential control circuit 5 amplifies an output signal from data input buffer 55 and applies complementary potentials to the two I/O lines constituting an I/O line pair.
These two I/O lines are connected electrically to only one sense amplifier provided corresponding to the pair corresponding to one column of the memory cells designated by column address signals CA0-CA(n-1) out of the bit line pairs BL, /BL in memory cell array 61. Therefore, the complementary potentials on the two I/O lines are transmitted to the two bit lines BL and /BL provided corresponding to one column of memory cells designated by column address signals CA0-CA(n-1) through one sense amplifier.
In memory cell array 61, only one word line WL provided corresponding to one row of memory cells designated by row address signals RA0-RA(n-1) has been activated. Therefore, potential of either one of the two I/O lines is supplied to one bit line BL or /BL connected to one (selected) memory cell MC which is arranged at an intersection of one column designated by column address signals CA0-CA(n-1) and one row designated by row address signals RA0-RA(n-1). Consequently, the external input data signal is written to the selected memory cell MC through the bit line BL or /BL which is connected thereto.
In the DRAM, data stored in each memory cell MC becomes extinct as time passes. In order to avoid such phenomenon, a so-called refreshing is carried out in which the same data as stored in each memory cell MC is automatically rewritten at every prescribed time period. The length of the prescribed period is shorter than the time necessary for the stored data of each memory cell to become extinct.
A refresh control circuit 51 and a refresh counter 52 are circuits provided for refreshing.
Refresh control circuit 51 instincts refresh counter 52 to output internal address signals Q0-Q(n-1) to.
Refresh counter 52 successively generates sets of address signals Q0-Q(n-1) representing respective addresses of the memory cells MCs in memory cell array 61 at every prescribed time period under control by refresh control circuit 51, when neither data writing to the memory cell MC of the address designated by external address signals A0-An nor data reading from the memory cell MC of the address designated by external address signals A0-An is carried out.
I/O control circuit 53 activates either one of data input buffer 55 or data output buffer 56 while it is receiving the signal An of the most significant bit from address buffer 54, and inactivates both data input buffer 55 and data output buffer 56 while it is not receiving the signal An of the most significant bit.
More specifically, in a period when external control signal /WE is at a low level, that is, when data is to be written to memory cell array 61, I/O control circuit 53 activates data input buffer 55. In the period when external control signal /WE is at a high level, that is, when data is to be read from memory cell array 61, I/O control circuit 53 activates data output buffer 56.
A particular circuit operation of address buffer 54 when neither data writing nor data reading to and from the memory cell MC designated by external address signals A0-An is to be carried out will be described.
Instead of external address signals A0-An, address signals Q0-Q(n-1) generated by refresh counter 52 are taken by address buffer 54. Address buffer 54 buffers the same and provides the resulting row address signals RA0-RA(n-1) and column address signals CA0-CA(n-1) to row decoder 58 and column decoder 57, respectively.
Column decoder 57, row decoder 58, sense amplifier group 60 and I/O line potential control circuit 5 carry out the same operation as in data reading from memory cell array 61 responsive to external address signals A0-An and the same operation as in data writing to memory cell array 61 responsive to external address signals A0-An, every time the output signal from address buffer 54 changes. Therefore, data stored in all memory cells MC in memory cell array 61 are successively refreshed in accordance with the addresses.
In such periods, the signal An of the most significant bit is not applied to I/O control circuit 53 from address buffer 54, and therefore data input buffer 55 and data output buffer 56 are inactive.
A bit line equalizer 59 electrically connects two bit lines BL and /BL constituting each bit line pair to equalize the potentials to an intermediate potential between high and low levels when neither data writing nor data reading based on external address signals A0-An and on address signals Q0-Q(n-1) generated by refresh counter 52 is carried out.
Similarly, in such a period, I/O line potential control circuit 5 electrically connects two I/O lines so as to make even the potentials thereof.
A clock generator 50 generates clock signals for controlling refresh control circuit 51, address buffer 54, column decoder 57, row decoder 58 and the like based on external control signals /RAS, /CAS, and /WE such that these circuits operate in the above described manner.
FIG. 11 is a partial circuit diagram showing the internal structure of the I/O gate.multidot.I/O line 62. FIG. 11 shows, as a representative, only a circuit portion provided corresponding to arbitrary two columns of memory cells in memory cell array 61.
Referring to FIG. 11, all sense amplifiers 610 are connected to a common sense amplifier driving circuit 620 in sense amplifier group 60.
Sense amplifier driving circuit 620 is controlled by a trigger signal .phi.s from clock generator 50 of FIG. 11 and drives all sense amplifiers 610 when data is to be written to memory cell array 61 and when data is to be read from memory cell array 61.
Each sense amplifier 610 is a differential amplifier connected to the two bit lines BL and /BL which are connected to the corresponding column of the memory cell.
I/O gate is constituted by an N channel MOS transistor T1 connected between each bit line BL and one of the two IO lines, and an N channel MOS transistor T2 connected between each bit line /BL and the other one of the I/O line /IO.
Gates of transistors T1 and T2 which are respectively connected to two bit lines BL and /BL provided corresponding to the same column of memory cells are connected to column decoder 57 of FIG. 10 through the same signal line CY. Column decoder 57 decodes column address signals CA0-CA(n-1) from address buffer 54 of FIG. 10, and sets to the high level only one of the signal lines CY which is connected to the gates of transistors T1 and T2 provided corresponding to the column of memory cells designated by the column address signals, and sets others to the low level. Consequently, only the two transistors T1 and T2 provided corresponding to the one column of the memory cells are turned ON, and two bit lines BL and /BL provided corresponding to the column of the memory cells are electrically connected to the two IO lines, that is, IO and /IO.
An I/O line equalizer 500 and an amplifying circuit 510 are included in I/O line potential control circuit 5 of FIG. 10. Twc I/O lines IO and /IO are both connected to I/O line equalizer 500 and amplifier circuit 510.
FIG. 12 is a circuit diagram showing the structure of I/O line equalizer 500.
Referring to FIG. 12, I/O line equalizer 500 includes two N channel MOS transistors T3 and T4 respectively connected between power supply Vcc and two I/O lines IO and /IO, and a P channel MOS transistor T5 and N channel MOS transistor T6 connected parallel to each other between two I/O lines IO and /IO.
A control signal /.phi..sub.w output from clock generator 50 of FIG. 10 is commonly applied to the gates of transistors T3 and T4.
Control signals .phi..sub.EQ and /.phi..sub.EQ having complementary potentials output from clock generator 50 of FIG. 10 are applied to the gate of transistor T5 and to the gate of transistor T6, respectively.
FIG. 13 is a circuit diagram showing a structure of amplifying circuit 510 of FIG. 11.
Referring to FIG. 13, amplifying circuit 510 is a current mirror type amplifier including a P channel MOS transistor T7 and N channel MOS transistors T9 and T11 connected in series between power supply Vcc and the ground Vss, and a P channel MOS transistor T8 and N channel MOS transistor T10 connected in parallel to transistors T7 and T9.
Gates of transistors T7 and T8 are connected to a node of transistors T7 and T9.
Gates of transistors T9 and T10 are connected to the two I/O lines IO and /IO of FIG. 11, respectively.
A control signal .phi..sub.P output from clock generator 50 of FIG. 10 is applied to the gate of transistor T11.
When data is written to memory cell array 61, an output potential of data input buffer 55 of FIG. 10 is applied to a connected point (a node N4) between transistors T8 and T10. When data is read from memory cell array 6, a potential .phi..sub.OUT of this node N4 is supplied as an output from the amplifying circuit 510 to data output buffer 56 of FIG. 10.
Circuit operation for reading data from memory cell array 61 of the DRAM will be described in greater detail with reference to FIGS. 11 to 15.
FIGS. 15(a) to 15 (l) comprise a timing chart showing potential changes at some nodes in the DRAM during data reading.
For convenience of description, output signal lines of bit lines, word lines, memory cells, sense amplifiers, transistors constituting the I/O gate and of column decoder 57 shown in FIG. 11 are denoted with reference characters in parenthesis ( ).
A circuit operation for successively reading data from memory cells MC1 and MC2 of FIG. 11 will be described as an example.
First, by row decoder 58, potential of one word line WL1 out of the word lines in memory cell array 61 is raised to a high level as shown in FIG. 14(a). Consequently, dependent on the data stored in each of the memory cells connected to the one word line WL1, potentials on bit lines connected to the memory cell changes.
FIG. 14 is a schematic diagram showing the structure of sense amplifier 610 and of memory cell MC. An arbitrary one column of memory cells is shown as a representative in FIG. 14.
Referring to FIG. 14, each memory cell MC includes an N channel MOS transistor TR and a capacitor C connected in series between the corresponding bit line BL or /BL and a low potential source such as the ground. The gate of transistor TR in each memory cell MC is connected to a word line WL corresponding to the memory cell MC. In each memory cell MC, the potential at the node of transistor TR and capacitor C corresponds to the data stored in the memory cell MC. More specifically, the stored data in each memory cell MC has the logic value of "1" and "0" when the potential at the node between the transistor TR and the capacitor C included therein is at a high level and at a low level, respectively.
Therefore, when one word line WL attains to a high level, the transistor TR is turned ON in each of the memory cells MC connected to the word line WL. Therefore, the potential of the bit line BL or /BL connected to each of memory cells MC out of the memory cells connected to the word line WL which store data "1" slightly increases because of the charges supplied from the capacitor C of the corresponding memory cell MC. The potential of the bit line BL or /BL connected to each of the memory cells MC connected to the word line WL which store data "0" slightly lowers because of the charges drawn to charge capacitor C of the corresponding memory cell MC.
In this manner, if a memory cell MC stores data "1", the potential of the bit line BL or /BL connected to this memory cell MC slightly increases in response to the rise of the potential of the word line WL connected to the memory cell MC. On the contrary, if the memory cell MC stores data "0", the potential of the bit line BL or /BL connected to the memory cell MC slightly lowers in response to the rise of the potential of the word line WL connected to the memory cell MC. In the period when neither data writing nor data reading is carried out to and from the memory cell array 61, the bit lines BL and /BL provided corresponding to each column of memory cells are set to the equal potential by the bit line equalizer 59 of FIG. 10. Therefore, when data is to be read, a slight potential difference is generated between the two bit lines BL and /BL provided corresponding to each column of memory cells in response to the rise of the potential of one word line WL.
Sense amplifier 610 includes a P channel MOS transistor 310 and an N channel MOS transistor 320 having their gates connected to the bit line BL, and a P channel MOS transistor 330 and an N channel MOS transistor 340 having their gates connected to the bit line /BL.
Transistors 310 and 320 are connected in series between signal lines 350 and 360 connected to sense amplifier driving circuit 620 of FIG. 11. Similarly, transistors 330 and 340 are connected in series between these signal lines 350 and 360.
In data reading, sense amplifier driving circuit 620 supplies supply potential and the ground potential to the signal lines 350 and 360, respectively, so as to drive all sense amplifiers 610.
Referring to FIG. 14, when the potential of bit line BL slightly increases at data reading, transistor 320 becomes a shallow conductive state (with large resistance value) in sense amplifier 610. Consequently, a voltage drop occurs at the gate connecting point of transistors 330 and 340 and at node N2. In response to the voltage drop, transistor 330 is also rendered to a shallow conductive. Consequently, voltage rises at gate connecting point between transistors 310 and 320 and at node N1. Because of the rise of potential, transistor 320 is rendered deep conductive, and lowers the potential at the gate connecting point of transistors 330 and 340 and at node N2 to the ground potential supplied to the signal line 360. In response, transistor 330 is also rendered to deep conductive, and the potential of node N1 rises to the supply potential supplied to the signal line 350. The potential at node N2 of transistors 310 and 320 and the potential at node N1 of transistors 330 and 340 are the outputs from sense amplifier 610.
In this manner, the potential of bit line BL is raised to the supply potential by means of sense amplifier 610, while the potential of bit line /BL is lowered to ground potential by the sense amplifier 610. Namely, the potential difference generated between bit lines BL and /BL is enlarged by means of the sense amplifier 610 to the difference voltage between the supply potential and the ground potential.
When the potential of bit line BL lowers slightly at data reading, transistor 310 in sense amplifier 610 is rendered shallow conductive in response, thus raises the potential of the gate connecting point of transistors 330 and 340. In response, transistor 340 is also rendered shallow conductive, and the potential at the gate connection point of transistors 310 and 320 lowers. Consequently, transistors 310 and 340 are rendered deep conductive, the potential of node N1 is lowered to the ground potential, and the potential at node N2 is raised to the supply potential.
In this manner, the potential of bit line BL is decreased to the ground potential by means of the sense amplifier 610, while the potential of bit line /BL is raised to the supply potential by means of the sense amplifier 610. Namely, in this case also, the slight potential difference generated between bit lines BL and /BL is enlarged to the difference voltage between the supply potential and the ground potential.
Referring to FIG. 11, assume that the data stored in memory cell MC1 and the data stored in memory cell MC2 are "1" and "0", respectively.
In response to the rise of the potential of the word line WL1 (See FIG. 15(a), potentials at bit lines BL1 and BL2 slightly rises and lowers, respectively, from the equalized potential, as shown in FIGS. 15(b) and (c). The potentials on bit lines /BL1 and /BL2 are maintained at the intermediate potential immediately after the rise of the potential on word line WL1, as shown in FIGS. 15(b) and (c).
Control signal .phi..sub.S attains to a high level immediately after the rise of the potential of the word line WL1 (see FIG. 15(d)). Sense amplifier driving circuit 620 drives all sense amplifiers 610 while the potential of the control signal .phi..sub.S is at the high level.
Therefore, the potentials on bit lines BL1 and /BL2 are raised to the supply potential in response to the rise of the potential of the control signal .phi..sub.S. The potentials of bit lines /BL1 and BL2 are decreased to the ground potential in response to the rise of the potential of the control signal .phi..sub.S.
After the control signal .phi..sub.S attains to the high level, the potentials of signal lines CY1 and CY2 are successively set to and maintained for a prescribed time period at a high level, as shown in FIGS. 15(f) and (g).
While the potential of signal line CY1 is at the high level, transistors T1-1 and T2-1 are ON. Therefore, potentials on I/O lines IO and /IO are determined by the potentials on bit lines BL1 and /BL1, respectively.
Similarly, while the potential of signal line CY2 is at the high level, transistors T1-2 and T2-2 are ON, and therefore potentials on I/O lines IO and /IO are determined by the potentials on bit lines BL2 and /BL2.
The potential of control signal /.phi..sub.W is always at the high level during data reading, as shown in FIG. 15(e). The potential of the control signal .phi..sub.EQ is maintained at the high level while the potential of any one of the output signal lines of column decoder 57 is at the high level as shown in FIG. 15(h), and accordingly, the potential of the control signal /.phi..sub.EQ is maintained at the low level while the potential of any one of the output signal lines of the column decoder 57 is at the high level as shown in FIG. 15(i).
Therefore, in data reading, the transistors T3 and T4 are ON in I/O line equalizer 500, and transistors T5 and T6 are OFF only when one of the output signal lines of column decoder 57 is at the high level.
Therefore, the I/O lines IO and /IO are fixed to the potential (Vcc-Vth) lower than the supply potential by the threshold voltage V.sub.TH of transistor T3 or T4, regardless of the output potentials of the sense amplifiers, when the potentials of the output signal lines of column decoder 57 are not at the high level. Therefore, immediately before the potential on signal line CY1 attains to the high level, the potential on the I/O line IO is lower than the potential of bit line BL1 by the threshold voltage Vth mentioned above, and potential of I/O line /IO is higher than the potential of bit line /BL1. Similarly, immediately before the potential of signal line CY2 attains to high level, the potential of I/O line IO is higher than the potential of bit line BL2 and the potential between I/O and IO is lower than the potential of bit line /BL2 by said threshold voltage V.sub.TH.
Therefore, when the potential of signal line CY1 attains to the high level, the potential on I/O line IO begins to rise to the supply potential because of the charges entering from bit line BL1, while the potential on I/O line /IO begins to lower toward the ground potential because of charges flowing out to bit line /BL1 (see FIG. 15(j)).
When the potential of signal line CY1 returns to the low level, transistors T5 and T6 turn ON in I/O line equalizer 500, and therefore, the potential of I/O line IO begins to lower, while the potential of I/O line /IO begins to rise. Finally, the potentials of I/O lines IO and /IO become equal to each other.
When the potential of signal line CY2 attains to the high level, transistors T5 and T6 are again turned OFF in I/O line equalizer 500. Therefore, because of the charges flowing out from the bit line I/O line IO to the bit line BL2, the potential of I/O line IO begins to lower to the ground potential, while the potential of I/O line /IO begins to rise because of the charges flowing in from bit line /BL2 to I/O line /IO.
When the potential of signal line CY2 returns to the low level, transistors T5 and T6 in I/O line equalizer 500 are again turned on. Therefore, the potentials of I/O lines IO and /IO rises and lowers, respectively, and finally, they are fixed at a potential lower than the supply potential by the respective threshold voltages V.sub.TH of transistors T3 and T4.
As shown in FIG. 15(k), control signal .phi..sub.P is kept at high level for a prescribed time period after any one of the output signal lines of column decoder 57 attains high level.
Namely, after the potentials of I/O lines IO and /IO begin to change dependent on the potentials on bit lines BL1 and /BL1 and after the potentials of I/O lines IO and /IO begin to change dependent on the potentials on bit lines BL2 and /BL2, transistor T11 turns ON in the amplifying circuit 510.
Referring to FIG. 13, when transistor T11 turns ON, one of the transistors T9 and T10 turns on dependent on the magnitude of the gate potentials of transistor T9 and T10, and thus supplies a current flowing through transistor T11 to the ground V.sub.SS.
More specifically, when the gate potential of transistor T9 is higher than the gate potential of transistor T10, transistor T9 turns on and supplies a current whose magnitude corresponds to the difference between these gate potentials to transistor T11. When the gate potential of transistor T10 is higher than the gate potential of transistor T9, transistor T10 turns ON and supplies a current whose magnitude corresponds to the difference between these gate potentials to transistor T11.
When transistor T9 turns on, the potential at node N3 lowers because of the current flowing through transistors T9 and T11 to the ground V.sub.SS. When the potential of node N3 becomes lower than the threshold voltage V.sub.TH of transistor T8, transistor T8 is rendered conductive and therefore, a current flowing from power supply V.sub.CC to the node N4 is generated. Meanwhile, since transistor T10 is OFF, the potential of node N4 is at the supply potential.
When transistor T10 is rendered conductive, the potential at node N4 lowers because of the current flowing from node N4 through transistors T10 and T11 to the ground V.sub.SS. Thus the potential at node N4 attains to a low level.
When control signal .phi..sub.P is at the low level, transistor T11 is OFF. Therefore, regardless of the gate potentials of transistors T9 and T10, potentials at nodes N3 and N4 are approximately at the supply potential.
Therefore, when the control signal .phi..sub.P attains a high level after the potential of signal line CY1 attains high level, the potential .phi..sub.OUT of node N4 is kept at the potential (supply potential) at which it has been kept, as shown in FIG. 15(l), since the gate potential of transistor T9 (potential of the I/O line IO) is higher than the gate potential (potential of I/O line /IO) of transistor T10. When the potential of the control signal .phi..sub.P attains to high level after the potential of signal line CY2 attains to the high level, the potential .phi..sub.OUT of node N4 begins to lower to a low potential as described above and shown in FIG. 15(l), since the gate potential of transistor T10 is higher than the gate potential of transistor T9.
Thereafter, when control signal .phi..sub.P returns to the low level, transistor T11 is turned off in the amplifying circuit 510, and thus the potential .phi..sub.OUT of node N4 returns to the supply potential.
In this manner, when the potential of the I/O line IO is increasing, the output potential .phi..sub.OUT of the amplifying circuit 510 attains to the high level, and when the potential of the I/O line IO is decreasing, it attains to the low level. Namely, when control signal .phi..sub.P is at the high level, the amplifying circuit 510 operates to output a potential whose level corresponds to the data stored in the selected memory cell MC1, MC2.
The length of the period in which the output signal line CY of column decoder 57 is maintained at the high level is set longer than the period from the potential difference between I/O lines IO and /IO begins to start until it reaches the maximum value V.sub.O.
As described above, in the conventional semiconductor memory device in which two bit lines are provided corresponding to each column of memory cells and data stored in a memory cell of the column of the memory cell is read utilizing the potential difference between the two bit lines, read data is provided by amplifying, by an amplifier, the potential difference generated between two. I/O lines when two I/O lines are connected to the two bit lines corresponding to the selected column of the memory cells.
Therefore, the earlier the timing of starting operation of the amplifier and the higher the speed of change of the output potential are in the amplifier, the shorter becomes the time from selection of one memory cell by the row decoder and the column decoder to the stabilization of the output potential of the amplifier corresponding to the data stored in the memory cell, that is, the shorter becomes the access time in data reading.
For example, in the DRAM shown in FIGS. 10-15, the earlier becomes the timing of the control signal .phi..sub.P to attain high level, the earlier the amplifying circuit 510 starts its operation. Therefore, the potential .phi..sub.OUT of the node N4 in the amplifying circuit 510 begins to change dependent on the potential difference between the I/O lines IO and /IO at an earlier timing.
More specifically, referring to FIG. 15, if the period from the time when potential of I/O line IO attains lower than the potential of I/O line /IO in response to the rise of the potential of control signal .phi..sub.EQ after the potential of CY2 attains high level, to the time when the potential of control signal .phi..sub.P attains to the high level, becomes shorter, the output potential .phi..sub.out of amplifying circuit 510 lowers more quickly to the potential corresponding to the data stored in memory cell MC2.
In the amplifying circuit 510, after the potential of control signal .phi..sub.P attains to the high level and the speed of change of the potential .phi..sub.out at node N4 is high, then the period .tau.2 becomes shorter in which period the amplifying circuit 510 starts its operation in response to the potential difference between the I/O lines IO and /IO generated by the control signal .phi..sub.EQ attaining high level after the potential of signal line CY2 has attained to the high level, and outputs a low level potential.
The speed of change of the output potential .phi..sub.out of the amplifying circuit 510 is also affected by the potential difference between I/O lines IO and /IO at the start of operation of the amplifying circuit 510.
More specifically, referring to FIG. 13, when transistor T11 is turned on with the gate potential of transistor T10 being sufficiently larger than the gate potential of transistor T9, the potential at node N4 quickly lowers to the low level, since a large current flows from node N4 through transistors T10 and T11 to the ground V.sub.SS. However, when the transistor T11 is turned ON with the gate potential of transistor T10 being slightly higher than the gate potential of transistor T9, the potential at node N4 lowers slowly to the low level, since a small current flows from node N4 through transistors T10 and T11 to the ground V.sub.SS.
In a conventional DRAM, during a period in which any one of the output signal lines of column decoder is at the high level, the potential difference between two I/O lines is very large. Therefore, the potential difference between the two I/O lines at the start of operation of the current mirror amplifier becomes small. This phenomenon will be described in detail with reference to FIGS. 11 to 13 and 15.
In both periods in which the signal line CY1 is at the high level and the signal line CY2 is at the high level, the potential difference between I/O lines IO and /IO reaches a very large value of the difference voltage V.sub.O between the supply potential and the ground potential, as shown in FIG. 15(j). Therefore, when the signal line CY1 attains the low level and then control signal .phi..sub.EQ attain the low level, it takes long to exchange charges between I/O lines IO and /IO through transistors T5 and T6. Consequently, the time .tau.1 necessary for the potentials of the I/O lines IO and /IO to be equal to each other becomes longer.
In the period when the signal line CY2 is at the high level, the potentials of the I/O lines IO and /IO must be the ground potential and the power supply potential, respectively, in response to the rise of control signal .phi..sub.EQ, contrary to the period in which the output signal line CY1 of the column decoder 57 is at the high level. However, since the time T1 necessary for the potential difference between I/O lines IO and /IO to reach zero from the fall of the potential of signal line CY1 is long, it takes long for the potential of the IO line IO and of /IO to reach the ground potential and to the power supply potential, respectively, in response to the rise of the control signal .phi..sub.EQ after the potential of signal line CY2 attains the high level.
Therefore, at the time when the control signal .phi..sub.P has risen to the high level after the potentials of the signal line CY2 and the control signal .phi..sub.EQ have both attained to the high level, the potential difference .DELTA.V between I/O lines IO and /IO is not large enough but still small. Therefore, in response to the rise of the control signal .phi..sub.P for reading data from memory cell MC2, the output potential .phi..sub.out of amplifying circuit 510 does not lower quickly but attains to the low level taking a long period of time T2.
As described above, when the data stored in the first and second memory cells which are read continuously are different from each other, if the time .tau.1 necessary for equalizing the potentials of the I/O lines IO and /IO is long, then the potential difference .DELTA.V between the I/O lines IO and /IO at the start of the operation of the amplifying circuit 510 for reading data from the second memory cell become small, and as a result, it takes long to read data from the second memory cell.
In order to avoid such phenomenon, the timing of rise of the control signal .phi..sub.P, that is, the timing of starting the operation of amplifying circuit 510 should be delayed to the time when the potential difference between the I/O lines IO and /IO becomes sufficiently large. By this method, the speed of change of the output potential .phi..sub.out of the amplifying circuit 510 is increased. Therefore, the time T2 necessary for the output potential .phi..sub.out of the amplifying circuit 510 to reach the potential corresponding to the data stored in the second memory cell from the rise of the control signal .phi..sub.P for reading data from the second memory cell becomes shorter. However, the time from when the potential of signal line CY2 attains to high level to when control signal .phi..sub.P attains to the high level for reading data from the second memory cell becomes longer. Therefore, the access time in data reading cannot be improved by this method.